For secure and efficient data transmission the increasing demand have created a need for hardware-based cryptographic solutions capable of providing high security with low resource utilization. However, existing software-based encryption techniques introduce computational overhead and increased execution latency, particularly in resource-constrained and high-speed embedded systems. To overcome these issues, this paper proposes a Field-Programmable Gate Array-Advanced Encryption Standard-128 (FPGA-based AES-128) cryptographic processor with resource optimization for secure data encryption and decryption. The proposed architecture implements the AES-128 using a 128-bit plaintext block and a 128-bit secret key. The encryption procedure contains key expansion, initial AddRoundKey, and ten encryption rounds, where every round incorporates the SubBytes, ShiftRows, MixColumns, AddRoundKey transformations. A round counter controls the sequential execution of the encryption operations, which is employed to reduce FPGA resource consumption. The proposed processor is designed and implemented on an FPGA platform, and its performance is evaluated in using proposed FPGA based AES-128 have the encryption throughput of 14,648 ps for ciphertext (128-bits). The cryptographic security and FPGA provide a secure data encryption.