Article Details
Optimized Booth Multiplier Architecture for High-Speed Arithmetic Applications
Author(s)
, Ramya R R
Abstract
Keywords
Modified Radix-4 Booth Multiplier, PPG, WTC, CLA, High Speed VLSI.
References
-
[1] Khamalesh Kumar Padmanabhan; Umadevi Seerengasamy; Abraham Sudharson Ponraj, Year: 2022, “High-Speed Grouping and Decomposition Multiplier for Binary Multiplication”, Electronics, Vol: 11, No: 24, pp. 4202.
-
[2] Tan Weihang; Antian Wang; Xinmiao Zhang; Yingjie Lao; Keshab K. Parhi, Year: 2023, “High-speed VLSI architectures for modular polynomial multiplication via fast filtering and applications to lattice-based cryptography”, IEEE Transactions on Computers, Vol: 72, No: 2, pp. 2454-2466.
-
[3] D. Bhuvana Suganthi; M. Shivaramaiah; A. Punitha; M. K. Vidhyalakshmi; S. Thaiyalnayaki, Year: 2023, “Design of 64-bit Floating-Point Arithmetic and Logical Complex Operation for High-Speed Processing”, In 2023 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), pp. 928-931.
-
[4] Thanikodi Manoj Kumar; Kasarla Satish Reddy; Stefano Rinaldi; Bidare Divakarachari Parameshachari; Kavitha Arunachalam, Year: 2021, “A low area high speed FPGA implementation of AES architecture for cryptography application”, Electronics, Vol: 10, No: 16, pp. 2023.
-
[5] Vu Trung Duong Le; Hoai Luan Pham; Thi Hong Tran; Thi Sang Duong; Yasuhiko Nakashima, Year: 2023, “Efficient and high-speed cgra accelerator for cryptographic applications”, In 2023 Eleventh International Symposium on Computing and Networking (CANDAR), pp. 189-195.
-
[6] Jeevan Battini; Sivani Kosaraju, Year: 2023, “Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units”, Silicon, Vol: 15, No: 2, pp. 993-1002.
-
[7] Padmanabhan Balasubramanian; Nikos E. Mastorakis, Year: 2024, “Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers”, Journal of Low Power Electronics and Applications, Vol: 14, No: 1.
-
[8] Pratibhadevi Tapashetti; Dr Rajkumar B. Kulkarni; Dr SS Patil, “Implementation of High Speed MAC VLSI Architectures, Based on High Radix Modified Booth Algorithm”, In International Conference on Advances In Electronics, Computer And Mathematical Sciences (ICIREMPS-2016) Sagar Institute of Research and Technology (SIRT) Bhopal, MP, India, Vol: 26.
-
[9] Muteen Munawar; Zain Shabbir; Muhammad Akram, Year: 2023, “Area, delay, and energy-efficient full Dadda multiplier”, Journal of Circuits, Systems and Computers, Vol: 32, No: 15, pp.2350258.
-
[10] Imran Ahmed Khan, Year: 2022, “Design and implementation of carbon nano-tube based full adder at 32nm technology for high speed and power efficient arithmetic applications”, In Journal of Physics: Conference Series, Vol: 2161, No: 1, pp. 012050.
-
[11] Cedomir Marangunic; Felipe Cid; Andrés Rivera; José Uribe, Year: 2022, “Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing”, Journal of VLSI circuits and systems”, Vol: 4, No: 01, pp. 42-51.
-
[12] O. J. M. Smith; F. de Mendonça; K. N. Kantor; A. A. Zaky; G. F. Freire, Year: 2022, “Ultra low potential operated fundamental arithmetic module design for high-throughput applications”, Journal of VLSI circuits and systems, Vol: 4, No: 01, pp. 52-59.
-
[13] Khamalesh Kumar Padmanabhan; Umadevi Seerengasamy; Abraham Sudharson Ponraj, Year: 2022, “High-speed grouping and decomposition multiplier for binary multiplication”, Electronics, Vol: 11, No: 24, pp. 4202.