Author(s) :
S. G. Priyadharshini, V. Kanagasubramanian, Masan Senthilkumar, Chintala Venkatesh
Article Name :
Efficient Low-Power Timing-Error Control in Digital Integrated Circuits Using Timing Error-Tolerant Circuits and Time-Borrowing Techniques
Abstract :
In modern digital systems, real-time operation of integrated circuits is of paramount importance. Presently, a significant portion of energy consumption is attributed to the overhead incurred by accommodating worst-case scenarios. This research proposes an energy-efficient timing-error control method employing a circuit designed to tolerate timing errors. The critical path is adept at identifying and correcting timing errors, particularly those causing irregular data transitions following the rising edge of the clock. Management of the transparent window of the clock is instrumental in swiftly addressing timing faults using minimal logic. A novel time-borrowing technique is introduced to account for future errors, applicable to locations with a short flip-flop setup time. The timing mistake occurs in two stages, and during second stage, an organized clock ensures a sufficiently extended transparent window, allowing for preservation of regular data without necessitating alterations to system clock. The study utilizes Razor Flip-flop and Adaptive Hold Logic to detect and recover from timing issues. This low-power timing-error control method provides an efficient means of mitigating the energy overhead associated with worst-case scenario margins in real-time digital systems.
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