In very large scale integration mainly focusing on three major constraints. That is Time delay, power consumption, Area of the circuit. In VLSI low power consumption devices has high demand in the market (Mobiles). In VLSI every component work in low supply voltage. Power consumption can be decreased two ways one statically and Dynamic voltage and frequency scaling (DVFS). If circuit complexity increased area will be increasing and power consumption also increases. In cascading circuits one circuit out-put fed into next circuit input. In this situation charge sharing, charge leakage problems exists. To overcome this problems zipper logic is used to the circuit, Zipper logic involves dividing the circuit into smaller sections and synchronizing their operations to minimize power consumption. By activating only necessary parts of the circuit. MGDI is required less number of transistors than compare to CMOS. In this paper half-adder, full adder re-designed using MGDI with ZIPPER logic by using DESIGN SCHEMATIC (for circuit designing) and MICRO-WIND TOOL for simulation in 65nm technology.