Multi-digit multiplication plays a vital role in modern digital systems, supporting applications such as numerical computation, chaos-based arithmetic, and hardware validation processes. With the increasing demand for high-speed data processing in areas like image processing and secure communication systems, there is a strong need for arithmetic units that achieve both high performance and low power consumption. This is particularly important in cryptographic applications where chaos-based techniques are employed for enhanced security. This work presents the hardware design and VLSI implementation of a multi-digit multiplier, focusing on optimizing area, speed, and energy efficiency. Novel compressor-based multiplier architecture is proposed to improve partial product reduction and minimize power dissipation. The design is evaluated in terms of performance metrics to ensure its suitability for advanced digital applications. Furthermore, the proposed architecture is adaptable for FPGA realization, providing flexibility in prototyping and practical deployment. The results offer significant guidance for system designers in selecting efficient multiplier structures for high-performance applications.